1. Field of the Invention
This invention relates generally to data conversion. In particular, this invention relates to an electronics circuit for the conversion of serial data into words of parallel bits suitable for assimilation by a computer.
2. Description of the Prior Art
Data in a serial format must first be converted into a parallel format before it can be applied to the input terminal of a computer. This conversion is generally accomplished by the use of a serial to parallel converter circuit. Such circuits of the prior art generally contain a storage register which stores a predetermined number of serial data bits therein. The aforementioned data bits are then read out in parallel and applied to the input terminal of a computer.
One such serial to parallel data converter of the prior art is disclosed in U.S. Pat. No. 3,395,400 to Russell G. DeWitt and John P. Forde. This serial to parallel data converter, in turn, includes a shift register for storing therein a predetermined number of serial data bits. Subsequent data of the input signal is then diverted to a store for a predetermined time during which the shift register is cleared. After the predetermined time, the diverted data bits are read into the shift register at a much higher rate than the bit rate of the input signal, and they are followed by the immediately following bits of the input signal.
A second serial to parallel data converter of the prior art is disclosed in U.S. Pat. No. 3,267,460 to F. M. Merrell and E. A. Herrera. This serial to parallel data converter, in turn, includes parallel mode means for producing an output word in the parallel mode, or for receiving a word in the parallel mode, or both; and serial mode means for producing an output word in the serial mode, or for receiving a word in the serial mode, or both. In addition, the aforementioned converter includes therein a first shift register connected between the parallel mode means and the serial mode means, and having a storage capacity of L bits, and a second shift register connected in parallel with the first shift register and having a storage capacity of B bits where B is a smaller number than L.
While the aforementioned devices of the prior art perform satisfactorily for their intended purpose, that of data conversion, these devices of the prior art ordinarily leave something to be desired, especially from the standpoints of complexity in design, data transmission speed, and cost effectiveness. In addition, the aforesaid devices of the prior art do not operate in the same manner as the subject invention, and contain a combination of elements that is somewhat different from that of the present invention.